logisim-evolution/logisim-evolution

help wanted pri +1 documentation

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

FlatLaf look and feel causes console warning about 10 hours ago

bug help wanted pri std good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Shiftregister resize nr. of stages gives an out of bounds error 1 day ago

bug help wanted investigating

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Feature Request: better mouse controls (zoom and panning) 2 days ago

enhancement help wanted pri -1 good first issue D'n'D required

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Random Generator limited to maximum of 32 bits 2 days ago

bug enhancement help wanted pri std all OS

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Ram and Dualport Ram test cases 4 days ago

enhancement help wanted pri std investigating good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Non-volatile not working on Dual Port RAM 4 days ago

bug help wanted good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Tikz picture export does not correctly display constant values 6 days ago

bug help wanted pri +1

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Window -> show toolbar does not function in current head 6 days ago

bug help wanted pri -1

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

System On a Chip simulation yield java.util.ConcurrentModificationException when executing a loaded ELF file in the Nios2s simulator 12 days ago

bug help wanted pri std

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Removing the "-93" switch when validating VHDL 15 days ago

enhancement help wanted

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

macOS app fails Gatekeeper; Homebrew cask deprecated and scheduled for disablement 16 days ago

enhancement help wanted macOS D'n'D required

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Undo/Redo not working while editing text labels / Undo manager registers editing of text without change 22 days ago

bug enhancement help wanted pri -1 all OS

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Cannot Pan with Middle-click in Circuit Appearance Editor 22 days ago

enhancement help wanted pri -1 good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Changing Splitter's fan out param resets custom bit mapping 22 days ago

enhancement help wanted pri -1 all OS

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

PlaRom in subcircuit makes clock stop working 24 days ago

bug help wanted pri -1 D'n'D required

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

defect [HDL]: HDL creation fails for Random generator component with 64bits 24 days ago

enhancement help wanted pri -1 investigating good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Specific fanout reduction causing out of bound exception 24 days ago

bug help wanted pri +1 all OS good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Save/load dialog box unresponsive when running through launcher on Windows; works when launching JAR directly. 26 days ago

help wanted investigating windows good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

User-selectable dark theme colors for HDL/assembly code editors 26 days ago

enhancement help wanted pri -1 good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Minor issues with the Preferences dialogue 27 days ago

enhancement help wanted pri -1 good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Shift-Register and Counter Appearance size do not match their content. 27 days ago

bug enhancement help wanted pri std

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Automatic import of logisim libraries instruction is outdated 27 days ago

help wanted documentation good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Remember camera position for each circuit 27 days ago

enhancement help wanted pri -1

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

SoC bus simulator not hiding traces 28 days ago

bug help wanted pri std good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

DRC-check on directory and file-names in the FPGA-commander 28 days ago

enhancement help wanted pri std

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

defect: [HDL] signed/unsigned setting of multiplier mixed up 28 days ago

help wanted pri std good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Text labels on canvas don't adapt to dark/light theme switch about 1 month ago

enhancement help wanted pri -1

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Obscure "Simulation halted by internal error" when using VHDL-circuits about 1 month ago

enhancement help wanted pri std good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Null pointer exception when enabling vhdl engine and not selecting the questasim tool-path about 1 month ago

bug help wanted pri std good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

dual port ram line-select octo-line mode does not work same as single-line mode about 1 month ago

bug help wanted pri std good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

What is telnet? about 1 month ago

enhancement help wanted pri -1 documentation good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Bug when using full view of VHDL console log -- no way back about 1 month ago

bug help wanted pri std good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Input window for decimal input on a pin broken about 1 month ago

bug help wanted pri -1 windows good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Appearance option for subcircuits is missing about 1 month ago

bug help wanted pri std all OS

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

defect: synthesizing Port I/O single pin about 2 months ago

bug help wanted pri std all OS good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

No way to save Timing Diagram data about 2 months ago

enhancement help wanted pri std documentation

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

VHDL Appearance property doesn't work as the Circuit Appearance property does. about 2 months ago

bug help wanted pri std all OS good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Deleting in Circuit Appearance editing does not notify listeners of a change in selection. about 2 months ago

help wanted pri std all OS good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

The attributes for a circuit are not always shown when the circuit is selected. about 2 months ago

bug help wanted pri std all OS

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Add the entries FpgaFreqPreDivider and FpgaFreqPreMultiplier in all the other fpga_*.properties files. about 2 months ago

enhancement help wanted pri std good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Add a writable EEPROM with persistent data capability 2 months ago

enhancement help wanted

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

TTL 7447: BI/RBO is not behaving according to data sheet 2 months ago

bug help wanted pri -1

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Format difference between TestVector and -tty table 2 months ago

enhancement help wanted pri std good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

English language strings scream for a cleanup 2 months ago

enhancement help wanted pri -1 good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Add weak outputs to sub-circuits 3 months ago

enhancement help wanted pri -1 triage

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Link to the documentation of the SoC library's DMA engine is broken in the Library Reference start page 3 months ago

help wanted pri std documentation good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Copy and Pasting feels very unintuitive 4 months ago

enhancement help wanted good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Dark themes are broken 4 months ago

bug help wanted pri -1 all OS good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Horizontal scroll wheel and touch pad not working to pan horizontally the drawing area on Linux 4 months ago

bug help wanted pri -1 linux good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Ability to buffer the output of the RGB Video component 4 months ago

enhancement help wanted pri -1

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Overcome the 7bit limit of Combinational analysis 4 months ago

enhancement help wanted pri std

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Timing diagram: Consider export to WaveDrom format 4 months ago

enhancement help wanted pri -1 good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Divider Error in Logism Evolution Version 4.1.0 5 months ago

bug help wanted pri +1 good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Issue with drag-selection and movement of sub-circuit appearance elements 5 months ago

bug help wanted pri std

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

[bug] I/O resource `SevenSegmentScanning` cannot be synthesized due to missing info in constraints file 5 months ago

help wanted pri std investigating linux windows good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

defect: [HDL] usage of >1 PortIO components 5 months ago

bug help wanted pri std good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Problem with the appearance of a sub-circuit V3.9 5 months ago

enhancement help wanted pri std all OS

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Fixing the Snapcraft package 5 months ago

help wanted pri std investigating linux good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Problem when editing viewed circuit's appearance in VHDL code mode 5 months ago

bug help wanted pri std good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Circuits can get deleted without confirmation 5 months ago

enhancement help wanted pri std good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Zooming with the mouse wheel moves the view 6 months ago

enhancement help wanted pri -1 all OS good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

The clock leaves trails when it is dragged while not oriented east 6 months ago

bug help wanted pri +1 all OS good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Documentation for Counter component doesn't match the "logism-evolution" appearance 6 months ago

help wanted documentation good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

AppImage 7 months ago

enhancement help wanted pri -1 linux good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

ROM Guide not up to date 7 months ago

help wanted pri std documentation good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Preloading several RAM memories when executing circuits from command line 7 months ago

enhancement help wanted pri std all OS

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

some TTLs not updating automatically (I guess) 8 months ago

bug help wanted pri std investigating good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Feature Request: Add more customization options for dynamic components in circuit appearance 8 months ago

enhancement help wanted pri -1

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Add Probe to the list of Dynamic Components 8 months ago

enhancement help wanted pri -1 good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Can't add components from a sub-sub-library 8 months ago

bug help wanted pri std all OS

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Menu rendering offset on KDE Wayland 8 months ago

bug help wanted pri -1 investigating linux

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

RGB Video ignores WIDTH/HEIGHT > 256 due to fixed backing image size 9 months ago

bug pri std all OS good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

GUI freezes for longer durations when switching between sub-circuits in large Logisim circuit designs 9 months ago

enhancement help wanted pri -1 all OS

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

New simulation core causes the SOC-simulator to stop working correctly at high tick-frequencies 10 months ago

bug help wanted pri +1 investigating

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Gradle: Debian and RPM package names are hard-coded for AMD64/x86_64 architecture 10 months ago

bug help wanted pri std linux good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Java logo on subwindows 10 months ago

enhancement help wanted pri -1 good first issue java

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Add option for default color of text from text tool. 10 months ago

enhancement help wanted pri -1 good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Logisim 4.0.0-dev not launching in Windows 10 10 months ago

bug help wanted pri -1 windows good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Add language support for Hebrew 11 months ago

enhancement help wanted good first issue

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Allow all Screen sizes and formats for the Video component. 11 months ago

enhancement help wanted pri -1

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Feature Request: VGA RGB Screen Component with Parallel Pixel Support 11 months ago

enhancement help wanted pri -1

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Display Bus Width on Input/Output Wires 11 months ago

AI Summary: Implement a feature in Logisim-evolution to display the bus width (number of bits) on input/output wires, similar to a previous Logisim version. This should be visually clear and ideally configurable by the user.

Complexity: 3/5

enhancement help wanted pri -1 D'n'D required

logisim-evolution/logisim-evolution

7.3K

Digital logic design tool and simulator

Java

#circuit#circuits#digital-circuit#digital-circuits#digital-logic#digital-logic-design#education#fpga#logic#logisim#logisim-evolution#simulator#timing-diagram#verilog#vhdl

Open Issues Need Help