Open Issues Need Help
View All on GitHub Create the first inference benchmark methodology about 3 hours ago
help wanted
Open-source AI inference chip from India — hardware, RTL, RISC-V, compiler, firmware, FPGA and ASIC development for contributors worldwide.
SystemVerilog
#ai-inference#asic#chip-design#fpga#india#open-source-hardware#risc-v
Choose and document the first FPGA target about 3 hours ago
help wanted hardware
Open-source AI inference chip from India — hardware, RTL, RISC-V, compiler, firmware, FPGA and ASIC development for contributors worldwide.
SystemVerilog
#ai-inference#asic#chip-design#fpga#india#open-source-hardware#risc-v
Add randomized RTL verification against the Python reference model about 3 hours ago
good first issue hardware
Open-source AI inference chip from India — hardware, RTL, RISC-V, compiler, firmware, FPGA and ASIC development for contributors worldwide.
SystemVerilog
#ai-inference#asic#chip-design#fpga#india#open-source-hardware#risc-v
Welcome contributors: introduce yourself and choose a workstream about 3 hours ago
good first issue
Open-source AI inference chip from India — hardware, RTL, RISC-V, compiler, firmware, FPGA and ASIC development for contributors worldwide.
SystemVerilog
#ai-inference#asic#chip-design#fpga#india#open-source-hardware#risc-v