The PML analyzer is an open source API providing a simple DSL to build a description of the architecture of your chip based on the PHYLOG Modelling Language (PML).

certification formal-languages formal-methods interference multi-core safety-critical
3 Open Issues Need Help Last updated: Jun 21, 2025

Open Issues Need Help

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AI Summary: Debug and fix the interference channel graph generation in the PML analyzer. The current implementation incorrectly links nodes, including unnecessary ones, due to not properly distinguishing transaction origins. The fix should ensure only relevant interference channels are represented, addressing the identified discrepancies between the theoretical and implemented graphs.

Complexity: 4/5
enhancement help wanted

The PML analyzer is an open source API providing a simple DSL to build a description of the architecture of your chip based on the PHYLOG Modelling Language (PML).

Scala
#certification#formal-languages#formal-methods#interference#multi-core#safety-critical

AI Summary: The task is to enhance the PML analyzer's Transaction class to allow creating a new Transaction from an existing one, while specifying a custom name for the new transaction. Currently, creating a Transaction from another only copies the name. The goal is to implement a constructor or method that accepts both an existing Transaction and a new name string.

Complexity: 2/5
enhancement good first issue

The PML analyzer is an open source API providing a simple DSL to build a description of the architecture of your chip based on the PHYLOG Modelling Language (PML).

Scala
#certification#formal-languages#formal-methods#interference#multi-core#safety-critical

AI Summary: Implement a 'write' operator in the PML analyzer's `onera.pmlanalyzer.pml.operators.Use` package, mirroring the existing 'read' operator. This operator should allow an Application to write to a set of Service providers, enabling a symmetrical representation of data flow.

Complexity: 4/5
enhancement good first issue

The PML analyzer is an open source API providing a simple DSL to build a description of the architecture of your chip based on the PHYLOG Modelling Language (PML).

Scala
#certification#formal-languages#formal-methods#interference#multi-core#safety-critical