Functional verification project for the CORE-V family of RISC-V cores.

risc-v systemverilog uvm verification
1 Open Issue Need Help Last updated: Jun 25, 2025

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AI Summary: The Verilator build for the CORE-V cv32e40p processor is failing due to multiple driver warnings on the `mm_ram.sv` module. The task is to resolve these warnings, likely by modifying the `mm_ram.sv` file to eliminate the conflicting assignments to several variables within the always_comb block. This involves understanding the Verilog code, identifying the conflicting assignments, and refactoring the code to ensure each variable is assigned by only one process.

Complexity: 4/5
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Functional verification project for the CORE-V family of RISC-V cores.

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#risc-v#systemverilog#uvm#verification