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View All on GitHub [HDL] Unit tests of VHDL/Verilog dataflow units about 2 months ago
enhancement good first issue nice-to-have
EPFL-LAP/dynamatic EPFL-LAP/dynamatic DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
Open project →
133
DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
VHDL
good first issue nice-to-have
EPFL-LAP/dynamatic EPFL-LAP/dynamatic DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
Open project →
133
DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
VHDL