ai-chip-design-platform good first issues (Python)

CONTRIBUTING.md should require a test that fails before the fix about 1 month ago

documentation good first issue

11

Multi-agent RISC-V verification and test-generation framework for AI-assisted RTL, ISS, compliance, coverage, and debug workflows.

Python

#agentic-ai#ai#chip-design#digital-design#eda#hardware-verification#machine-learning#multi-agent-systems#red-teaming#riscv#rtl#simulation#systemverilog#verification#verilog

Audit except Exception handlers that hide programming errors about 1 month ago

good first issue silent-failure tech-debt

HUNT-001/ai-chip-design-platform

11

Multi-agent RISC-V verification and test-generation framework for AI-assisted RTL, ISS, compliance, coverage, and debug workflows.

Python

#agentic-ai#ai#chip-design#digital-design#eda#hardware-verification#machine-learning#multi-agent-systems#red-teaming#riscv#rtl#simulation#systemverilog#verification#verilog

Test fixtures are built from implementations, not schemas about 1 month ago

enhancement help wanted test-gap

HUNT-001/ai-chip-design-platform

11

Multi-agent RISC-V verification and test-generation framework for AI-assisted RTL, ISS, compliance, coverage, and debug workflows.

Python

#agentic-ai#ai#chip-design#digital-design#eda#hardware-verification#machine-learning#multi-agent-systems#red-teaming#riscv#rtl#simulation#systemverilog#verification#verilog

Producers emit drifted status vocabulary at phase level about 1 month ago

bug good first issue area: schema

HUNT-001/ai-chip-design-platform

11

Multi-agent RISC-V verification and test-generation framework for AI-assisted RTL, ISS, compliance, coverage, and debug workflows.

Python

#agentic-ai#ai#chip-design#digital-design#eda#hardware-verification#machine-learning#multi-agent-systems#red-teaming#riscv#rtl#simulation#systemverilog#verification#verilog

HUNT-001/ai-chip-design-platform

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