Open Issues Need Help
View All on GitHub Expand the SystemVerilog parser to handle the relatively expressive system verilog syntax 28 days ago
help wanted
KwachOjunga/pliron-circt KwachOjunga/pliron-circt An MLIR-based compiler infrastructure spanning multiple abstraction levels of hardware representation, transformation, and RTL generation
Open project →
0
An MLIR-based compiler infrastructure spanning multiple abstraction levels of hardware representation, transformation, and RTL generation
Rust