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OpenCoreLabsX/TDRV32 OpenCoreLabsX/TDRV32 Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
Open project →
0
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog
asic: publish a reproducible OpenLane PPA report 3 months ago
help wanted asic
OpenCoreLabsX/TDRV32 OpenCoreLabsX/TDRV32 Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
Open project →
0
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog
help wanted ci
OpenCoreLabsX/TDRV32 OpenCoreLabsX/TDRV32 Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
Open project →
0
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog
fpga: validate the current DE2-115 flow on hardware 3 months ago
help wanted fpga
OpenCoreLabsX/TDRV32 OpenCoreLabsX/TDRV32 Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
Open project →
0
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog
docs: add an architecture and pipeline block diagram 3 months ago
documentation good first issue
OpenCoreLabsX/TDRV32 OpenCoreLabsX/TDRV32 Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
Open project →
0
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog