Open Issues Need Help
View All on GitHub verification: review precise traps under stalls and backpressure about 2 hours ago
help wanted verification
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog
asic: publish a reproducible OpenLane PPA report about 2 hours ago
help wanted asic
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog
ci: avoid rebuilding the tool image for RTL-only pull requests about 2 hours ago
help wanted ci
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog
fpga: validate the current DE2-115 flow on hardware about 2 hours ago
help wanted fpga
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog
docs: add an architecture and pipeline block diagram about 2 hours ago
documentation good first issue
Open-source five-stage RV32IMC RISC-V processor core written in SystemVerilog, with simulation and formal verification.
SystemVerilog
#asic#cocotb#cpu-core#formal-verification#fpga#open-source-hardware#risc-v#rtl#rv32imc#systemverilog