OpenCoreLabsX

OpenCoreLabsX/apb-timer-core

APB-based TIMER core with PWM mode support for SoC and embedded system integration.

1 good first / help-wanted issue · SystemVerilog · last activity Jul 6, 2026

1 stars 0 forks 1 watchers SystemVerilog MIT License
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1 Open Issue Need Help Last updated: Jul 6, 2026

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[dv] Add boundary-condition regression for timer and PWM 3 months ago
enhancement good first issue help wanted
OpenCoreLabsX/apb-timer-core
1

APB-based TIMER core with PWM mode support for SoC and embedded system integration.

SystemVerilog