OpenCoreLabsX

OpenCoreLabsX/apb-usart-core

APB-based USART controller for SoC and embedded system integration.

1 good first / help-wanted issue · SystemVerilog · last activity Jul 1, 2026

0 stars 0 forks 0 watchers SystemVerilog MIT License

1 Open Issue Need Help Last updated: Jul 1, 2026

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[dv] Implement a serial monitor and error-injection regression 3 months ago

enhancement help wanted

OpenCoreLabsX/apb-usart-core

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APB-based USART controller for SoC and embedded system integration.

SystemVerilog