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OpenSiliconHub/SUBLEQ-CPU

Minimal SUBLEQ CPU in both Verilog and VHDL, Guide to build your own SUBLEQ CPU.

1 good first / help-wanted issue · VHDL · last activity Jul 1, 2026

1 stars 0 forks 1 watchers VHDL Apache License 2.0

cpu fpga oisc subleq verilog

1 Open Issue Need Help Last updated: Jul 1, 2026

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Add Testbenches for All Individual Modules 4 months ago

good first issue

OpenSiliconHub/SUBLEQ-CPU

1

Minimal SUBLEQ CPU in both Verilog and VHDL, Guide to build your own SUBLEQ CPU.

VHDL

#cpu#fpga#oisc#subleq#verilog