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View All on GitHubAMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AI Summary: Implement an atomic XOR operation within the Iris Triton-based RMA library, mirroring the functionality of Triton's existing atomic operations. This involves adding a new function to the Iris API that performs an atomic logical XOR on a specified memory location.
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AI Summary: Implement an atomic_or function within the Iris Triton-based RMA library, mirroring the functionality of Triton's existing atomic operations. This involves adding the functionality to the Iris API, ensuring compatibility with existing code and testing its correctness and performance.
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AI Summary: Implement an atomic minimum operation (`atomic_min`) within the Iris Triton-based RMA library, mirroring the functionality provided by Triton's existing atomic operations. This involves extending Iris's API to include this new function and ensuring its correct and efficient implementation within the multi-GPU context.
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AI Summary: Implement an atomic_max function within the Iris Triton-based RMA library, mirroring the functionality of Triton's existing atomic operations. This involves adding a new function to the Iris API that performs an atomic maximum operation on a specified memory location.
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AI Summary: Implement an atomic_and function within the Iris Triton-based RMA library, mirroring the functionality of Triton's existing atomic operations. This involves adding a new function to the Iris API that performs an atomic logical AND operation on a specified memory location.
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AI Summary: Make the currently private Iris HIP module public, allowing users to directly access its convenience functions (like `get_wall_clock_rate`) instead of going through the main Iris API. This involves changing the module's visibility and potentially updating documentation.
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AI Summary: Refactor the GEMM + All-Scatter example in the Iris project to remove an unnecessary inner loop and restructure the communication to handle the full GEMM tile in a single operation. This involves removing redundant code and potentially rewriting the communication logic for improved efficiency.
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming
AI Summary: Implement a producer-consumer example in Triton using Iris for multi-GPU communication. The example should utilize separate HIP streams for producer and consumer kernels, atomic signaling for synchronization, and demonstrate per-block synchronization using flags in shared memory. The code should handle data transfer between two GPUs using `iris.store` and `iris.load`.
AMD RAD's multi-GPU Triton-based framework for seamless multi-GPU programming