UTOSS

UTOSS/risc-v

UTOSS' 5-stage pipelined RISC-V core.

10 stars 13 forks 10 watchers SystemVerilog CERN Open Hardware Licence Version 2 - Strongly Reciprocal
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19 Open Issues Need Help Last updated: Jul 8, 2026

Open Issues Need Help

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Extract the `extend` module from the instruction decoder about 1 month ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Use SV interfaces for memory interfaces about 1 month ago
good first issue de
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Implement `Zbs` sub-extension ALU 3 months ago
good first issue de
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Add register type 5 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Implement rotation operations of `Zbb` spec 5 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Convert ALU control into enum 6 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Implement bit count operations of `Zbb` 6 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Implement logic + min/max + sign ext parts of `Zbb` 6 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Implement `Zba` sub-extension ALU 6 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Implement `Zbb` sub-extension ALU 7 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Make SVlint run for our dut.sv 7 months ago
good first issue ci dx
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
DE1-SoC env: implement HEX displays MMIO 7 months ago
good first issue track:fpga:de1-soc
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Convert CFSM params to an enum 7 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Review RISCOF's `RV32I` failures 9 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Use `alu_op_t` in CFSM 10 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Simplify decoding 10 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Improve memory loader module 10 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Extract RF module from instruction decoder 10 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog
Move ALU source selection to decoder 12 months ago
good first issue
UTOSS/risc-v
10

UTOSS' 5-stage pipelined RISC-V core.

SystemVerilog