abhay2004-rgb/RAM-ha

1 Open Issue Need Help Last updated: Jul 17, 2025

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🧠 2-bit 4-location RAM – Digital Memory Design This project involves the design and simulation of a 2-bit wide, 4-location Random Access Memory (RAM) using Verilog HDL. It is a compact memory model designed to demonstrate the working of digital memory blocks typically found in processor cache or embedded systems. Each memory location stores a 2-bit value, and there are four such locations addressable via a 2-bit address input. The memory supports synchronous write (controlled by clock and write enable) and asynchronous read, enabling users to understand key concepts of memory timing and control. This project serves as a foundational module for learning digital system design and is ideal for beginners working with FPGAs, memory modeling, or VLSI design. about 2 months ago

AI Summary: Design and simulate a 2-bit wide, 4-location Random Access Memory (RAM) using Verilog HDL. The RAM should support synchronous write operations (controlled by clock and write enable) and asynchronous read operations. This project aims to demonstrate fundamental digital memory concepts.

Complexity: 3/5

help wanted good first issue

abhay2004-rgb/RAM-ha