Open Issues Need Help
View All on GitHubAI Summary: This issue requests the creation of a "Self Reloading Counter" feature. The linked README file likely contains specific implementation details and requirements for this counter, which is tagged as a "good first issue" and eligible for Hacktoberfest.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of an "APB system" with detailed specifications provided in a linked README file. The bounty and labels suggest it's a well-defined task suitable for new contributors, potentially related to the Hacktoberfest event.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of an APB (Advanced Peripheral Bus) slave component. The provided link likely contains detailed specifications and requirements for implementing this hardware interface.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue is a placeholder to create a "master" APB (presumably a project or component) and directs contributors to a README file for further details. The bounty and labels suggest it's an introductory task suitable for newcomers and Hacktoberfest participants.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of an edge detector, with detailed instructions available via a provided GitHub link. The bounty and 'good first issue' label suggest it's a beginner-friendly task, likely involving image processing techniques.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of a 2:1 multiplexer, a fundamental digital logic component. The linked README likely contains detailed specifications and requirements for its implementation. It's marked as a 'good first issue' and eligible for Hacktoberfest, suggesting it's a beginner-friendly task.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the design of a simple Arithmetic Logic Unit (ALU). The linked README file likely contains specific requirements and details for the ALU's functionality and implementation.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of a binary to one-hot encoding converter. The linked README.md likely contains specific implementation details and requirements for this conversion tool.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of an "Odd counter" feature. The linked README file likely contains detailed specifications and requirements for implementing this counter.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of a parallel-to-serial converter. The linked README file likely contains detailed specifications and requirements for this hardware or software implementation. It's labeled as a 'good first issue' and eligible for Hacktoberfest, suggesting it's suitable for beginners.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the design of a synchronous First-In, First-Out (FIFO) buffer. The linked README file likely contains the specific requirements and constraints for this design.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of different "flavors" of multiplexers, as detailed in a linked README file. The bounty and labels suggest it's a beginner-friendly task suitable for Hacktoberfest.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the design of a simple memory interface. The linked README.md likely contains specific requirements and constraints for this design, which is tagged as a 'good first issue' and eligible for Hacktoberfest.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of a Round Robin arbiter. The provided link likely contains specific implementation details and requirements for this arbiter, which is a common pattern for distributing tasks or requests fairly among multiple entities.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of a program that converts binary numbers into their Gray code equivalents. The linked README file likely contains specific requirements and examples for this conversion.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of a 'Sequence Detector' module. The provided link leads to a README file which presumably contains the detailed specifications and requirements for this module. The bounty and labels suggest it's a beginner-friendly task suitable for Hacktoberfest.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of a module to identify the position of the second set bit (from the least significant bit) within an N-bit vector. The provided link likely contains more detailed specifications and constraints for the implementation.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the design of a shift register. The linked README.md likely contains detailed specifications for the implementation, but based on the title alone, it involves understanding and potentially implementing a fundamental digital logic component.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the implementation of a Linear Feedback Shift Register (LFSR). The linked README.md likely contains specific requirements and details for the LFSR's functionality and design.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of a Fixed Priority Arbiter. The linked README file likely contains detailed specifications and requirements for this arbiter, which is a component used in managing access to a shared resource based on predefined priorities.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)
AI Summary: This issue requests the creation of different variations of a D-Flip-Flop, a fundamental digital logic circuit. The linked README likely contains specific details on the types of D-Flip-Flops to be implemented, potentially including synchronous, asynchronous, or edge-triggered versions.
A SystemVerilog playground for Hacknight 7.0 featuring 21 standalone hardware design modules. (Forked from https://github.com/pranav0x0112/Twenty-One-Pilots)