chipsalliance/verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

1.6K stars 250 forks 1.6K watchers C++ Other

analysis formatter hacktoberfest language-server-protocol lexer linter lsp-server parser productivity style-linter sv-lrm syntax-tree systemverilog systemverilog-developer systemverilog-parser verible yacc

View on GitHub Website

1 Open Issue Need Help Last updated: Sep 15, 2025

Open Issues Need Help

View All on GitHub

Flex and Bison toolchain switching stopped working with bazel 8 about 1 month ago

help wanted

chipsalliance/verible

1.6K

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

C++

#analysis#formatter#hacktoberfest#language-server-protocol#lexer#linter#lsp-server#parser#productivity#style-linter#sv-lrm#syntax-tree#systemverilog#systemverilog-developer#systemverilog-parser#verible#yacc