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chipsalliance/verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

3 good first / help-wanted issues · C++ · last activity Sep 15, 2025

1.6K stars 250 forks 1.6K watchers C++ Other
analysis formatter hacktoberfest language-server-protocol lexer linter lsp-server parser productivity style-linter sv-lrm syntax-tree systemverilog systemverilog-developer systemverilog-parser verible yacc
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3 Open Issues Need Help Last updated: Sep 15, 2025

Open Issues Need Help

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Missing space before hashtag in typedef declaration of parameterized class 2 months ago
good first issue formatter opentitan
chipsalliance/verible
1.6K

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

C++
#analysis#formatter#hacktoberfest#language-server-protocol#lexer#linter#lsp-server#parser#productivity#style-linter#sv-lrm#syntax-tree#systemverilog#systemverilog-developer#systemverilog-parser#verible#yacc
Flex and Bison toolchain switching stopped working with bazel 8 3 months ago
help wanted
chipsalliance/verible
1.6K

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

C++
#analysis#formatter#hacktoberfest#language-server-protocol#lexer#linter#lsp-server#parser#productivity#style-linter#sv-lrm#syntax-tree#systemverilog#systemverilog-developer#systemverilog-parser#verible#yacc
[kythe] Output to file capability 4 months ago
good first issue kythe
chipsalliance/verible
1.6K

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

C++
#analysis#formatter#hacktoberfest#language-server-protocol#lexer#linter#lsp-server#parser#productivity#style-linter#sv-lrm#syntax-tree#systemverilog#systemverilog-developer#systemverilog-parser#verible#yacc