kebag-logic

kebag-logic/milan-fpga

FPGA implementation of Milan Specs v1.2

3 good first / help-wanted issues · SystemVerilog · last activity Jul 24, 2026

9 stars 2 forks 9 watchers SystemVerilog CERN Open Hardware Licence Version 2 - Weakly Reciprocal

3 Open Issues Need Help Last updated: Jul 24, 2026

Open Issues Need Help

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Auto-generate register memory map instead of maintaining it manually 9 days ago

enhancement good first issue

kebag-logic/milan-fpga

9

FPGA implementation of Milan Specs v1.2

SystemVerilog

docs: add CONTRIBUTING/house-style doc + complete TESTING.md (behave tier + CERT suites) 3 months ago

documentation good first issue

kebag-logic/milan-fpga

9

FPGA implementation of Milan Specs v1.2

SystemVerilog

docs: complete FPGA_DESIGN.md module map (~55 missing) + tb/verilator suite table 3 months ago

documentation good first issue

kebag-logic/milan-fpga

9

FPGA implementation of Milan Specs v1.2

SystemVerilog