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View All on GitHub Use riscv-dv for randomized core testing about 2 hours ago
AI Summary: This issue proposes integrating `riscv-dv`, an instruction generator, to enable randomized testing of RISC-V cores. The existing Verilator and Cocotb simulation environment would be adapted to execute these generated tests. Verification will involve comparing the execution results against a reference model, such as the Sail RISC-V model, to ensure correctness.
Complexity:
4/5
good first issue tests
RISC-V out-of-order core for education and research purposes
Python
#risc-v#riscv