kuznia-rdzeni

kuznia-rdzeni/coreblocks

RISC-V out-of-order core for education and research purposes

92 stars 27 forks 92 watchers Python Other
risc-v riscv
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15 Open Issues Need Help Last updated: Jul 1, 2026

Open Issues Need Help

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Store Verilated artifacts in CI about 2 hours ago
enhancement good first issue infrastructure
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
More detailed synthesis reports in CI 3 days ago
good first issue infrastructure
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Clean up bus abstraction layer 8 days ago
good first issue refactor
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
tiny config is not working 10 days ago
bug good first issue
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Implement RVVI 20 days ago
enhancement good first issue nlnet
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Use riscv-dv for randomized core testing about 1 month ago
good first issue tests priority
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Add verification with Litex to the CI about 1 month ago
good first issue infrastructure
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Build Docker containers in CI and move to separate repo about 2 months ago
good first issue infrastructure nice to have
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Allow assembly tests to finish before the time limit about 2 months ago
enhancement good first issue tests
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Accept custom `CoreConfiguration` in `gen_verilog` script 2 months ago
enhancement good first issue nice to have
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Implement Physical Memory Protection (PMP) 4 months ago
enhancement good first issue
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Make PipelinedMul available as a configuration 4 months ago
enhancement good first issue
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Add OpenLane synthesis to CI 4 months ago
good first issue infrastructure
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Check for CRLF line endings in CI formatting runs 4 months ago
good first issue infrastructure
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Implement Zbkx 4 months ago
enhancement good first issue
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv