kuznia-rdzeni

kuznia-rdzeni/coreblocks

RISC-V out-of-order core for education and research purposes

28 good first / help-wanted issues · Python · last activity Jul 1, 2026

92 stars 27 forks 92 watchers Python Other
risc-v riscv
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28 Open Issues Need Help Last updated: Jul 1, 2026

Open Issues Need Help

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Possible TLB invalidation bug about 1 hour ago
bug help wanted
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
remove "good first issue" label and replace it with a custom "good initial issue" about 4 hours ago
good first issue
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
test_fpu_mul.TestMul test does not pass on ARM about 4 hours ago
bug good first issue tests
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
mcountinhibit missing about 4 hours ago
enhancement good first issue
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
push_gh-pages fails on master branch on forks 1 day ago
good first issue infrastructure
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Decoder rework 11 days ago
good first issue nice to have refactor performance
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
write to `mtime` MMIO is not immedietally visible in `time` CSR (even after fence) 11 days ago
good first issue question
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
implement Zimop, Zcmop extensions 12 days ago
enhancement good first issue nice to have
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Add benchmarks for S-mode (non BARE translation modes) 18 days ago
good first issue infrastructure nice to have
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Add benchmark cycle run time to graphs about 2 months ago
good first issue infrastructure
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Store Verilated artifacts in CI 2 months ago
enhancement good first issue infrastructure
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Use riscv-dv for randomized core testing 2 months ago
good first issue tests priority
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Replace parameterized with pytest.mark 3 months ago
good first issue tests refactor
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Use SimpleTestCircuit where applicable 3 months ago
good first issue tests refactor
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Run tests in loop 3 months ago
good first issue tests nice to have
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
More detailed synthesis reports in CI 3 months ago
good first issue infrastructure
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Clean up bus abstraction layer 4 months ago
good first issue refactor
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
tiny config is not working 4 months ago
bug good first issue
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Implement RVVI 4 months ago
enhancement good first issue nlnet
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Add verification with Litex to the CI 5 months ago
good first issue infrastructure
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Build Docker containers in CI and move to separate repo 5 months ago
good first issue infrastructure nice to have
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Allow assembly tests to finish before the time limit 5 months ago
enhancement good first issue tests
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Accept custom `CoreConfiguration` in `gen_verilog` script 6 months ago
enhancement good first issue nice to have
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Implement Physical Memory Protection (PMP) 7 months ago
enhancement good first issue
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Make PipelinedMul available as a configuration 8 months ago
enhancement good first issue
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Add OpenLane synthesis to CI 8 months ago
good first issue infrastructure
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Check for CRLF line endings in CI formatting runs 8 months ago
good first issue infrastructure
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv
Implement Zbkx 8 months ago
enhancement good first issue
kuznia-rdzeni/coreblocks
92

RISC-V out-of-order core for education and research purposes

Python
#risc-v#riscv