Open Issues Need Help
View All on GitHub [doc] Add human-readable names and descriptions to remaining blocks about 2 months ago
Component:Doc Good First Issue Earlgrey-PROD Triaged
lowRISC/opentitan lowRISC/opentitan OpenTitan: Open source silicon root of trust
Open project →
3.6K
OpenTitan: Open source silicon root of trust
SystemVerilog
[Verilator] Unable to connect to virtual JTAG port with OpenOCD about 2 months ago
Component:Tooling Help Wanted
lowRISC/opentitan lowRISC/opentitan OpenTitan: Open source silicon root of trust
Open project →
3.6K
OpenTitan: Open source silicon root of trust
SystemVerilog
Good First Issue Earlgrey-PROD Triaged
lowRISC/opentitan lowRISC/opentitan OpenTitan: Open source silicon root of trust
Open project →
3.6K
OpenTitan: Open source silicon root of trust
SystemVerilog
Good First Issue Priority:P3 Component:RTL IP:kmac Type:Icebox Earlgrey-PROD Triaged
lowRISC/opentitan lowRISC/opentitan OpenTitan: Open source silicon root of trust
Open project →
3.6K
OpenTitan: Open source silicon root of trust
SystemVerilog
[util/design] Create a make-ip script that generates directory structure and boilerplate files 5 months ago
Good First Issue Help Wanted Priority:P3 Type:Enhancement Type:FutureRelease Earlgrey-PROD Triaged
lowRISC/opentitan lowRISC/opentitan OpenTitan: Open source silicon root of trust
Open project →
3.6K
OpenTitan: Open source silicon root of trust
SystemVerilog