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View All on GitHub [BUG] frontend drops the RAS call-push / return-pop when a call or return in the upper fetch slot follows a not-taken branch in the lower slot about 2 months ago
Component:RTL Type:Bug Good First Issue Status:In Progress CV32A65X
openhwgroup/cva6 openhwgroup/cva6 The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
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The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Assembly
#ariane#asic#cpu#fpga#risc-v#rv64gc#systemverilog-hdl
Type:Bug Good First Issue Status:In Progress Component:APU
openhwgroup/cva6 openhwgroup/cva6 The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Open project →
3.1K
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Assembly
#ariane#asic#cpu#fpga#risc-v#rv64gc#systemverilog-hdl
[BUG] frontend/instr_scan incorrectly decodes reserved C.JR and C.EBREAK as valid RVC jump instructions 3 months ago
Component:RTL Status:Resolved Type:Bug Good First Issue
openhwgroup/cva6 openhwgroup/cva6 The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Open project →
3.1K
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Assembly
#ariane#asic#cpu#fpga#risc-v#rv64gc#systemverilog-hdl
64 bit addresses must have bits 63-39 cleared 4 months ago
Component:RTL Type:Bug Good First Issue Status:New notCV32A65X
openhwgroup/cva6 openhwgroup/cva6 The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Open project →
3.1K
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Assembly
#ariane#asic#cpu#fpga#risc-v#rv64gc#systemverilog-hdl