tommythorn/simmerv

AI Summary: This issue proposes adding support for the Svinval extension, which introduces three new instructions for fine-grained TLB invalidation. In an emulator context without a physical TLB, these instructions can be simplified to no-ops or existing equivalents, making the implementation relatively straightforward. This enhancement is part of a larger effort to achieve full RVA22 support.

AI Summary: This issue proposes adding support for Zihpm, a hardware performance monitor counter extension, to an emulator. The core change involves modifying the CSR (Control and Status Register) handling to allow reads from specific performance counter registers to return 0 and writes to be ignored, without triggering illegal instruction exceptions. Access control for U/S-mode reads will also need to be implemented based on `mcounteren` and `scounteren`.

AI Summary: This issue proposes adding three RISC-V extensions: Zicbom (cache block management), Zicbop (cache block prefetch), and Zicboz (cache block zero). For emulation, most instructions are no-ops, but `cbo.zero` requires actual memory zeroing of a 64-byte cache block.

AI Summary: This issue proposes adding the Zbs extension to the RISC-V instruction set, which introduces eight new single-bit manipulation instructions. The implementation involves modifying several core files related to instruction decoding and execution, following a pattern established by a previous extension.

AI Summary: This GitHub issue describes an investigation into the `Emulator::tick()` function, specifically the parameter passed to it (e.g., `self.tick(40)`). This parameter controls the coupling between the emulated CPU and other system functions. The user experimented with various values to characterize a known bug where certain parameters cause the emulated Linux to hang, documenting different boot behaviors and specific freeze points.

AI Summary: This issue proposes adding support for 'Zbc', which is expected to be a straightforward enhancement. The contributor suggests modeling the implementation after the existing 'Zba' support, indicating a clear pattern to follow. It's labeled as a 'good first issue', further reinforcing its simplicity.

AI Summary: This issue proposes adding support for 'Zbb', which is expected to be a straightforward enhancement. The task can be modeled after the existing implementation for 'Zba', suggesting a clear path for development and integration.

AI Summary: This issue proposes integrating and enabling Tenstorrent's RISC-V architecture tests. The current tests require enhancements, specifically for more memory regions and minimal support for V instructions to clear state.

AI Summary: This issue proposes an optimization for the tree decoder in Rust. Instead of dynamically traversing the tree, the goal is to generate Rust code that uses match statements, which is expected to improve performance.