Verilog good first issues

This issue proposes the creation of an IP checker utility to identify common design problems in imported IP blocks for OpenROAD. The utility would validate LEF and LIB files against a predefined list of checks, aiming to prevent downstream issues and improve root-cause analysis.

The user is investigating why a design mapped to Yosys's generic gates requires more FPGA primitives (L2T4 LUT-trees) than expected, suggesting a potential underperformance in the translation process. They are requesting the P&R log to include the final utilization of L2T4 LUT-tree primitives to better understand the mapping.

This is a feature tracker for the 'ram' tool, outlining planned enhancements. Key features include support for endcap insertion, physical verification, arbitrary array and bit mask sizes, wider AND gates in decoders, automatic master and followpin layer/width selection, cell anchoring, and user-configurable input/output buffers.

The user is reporting a high-pitched crackling sound issue specifically with the main theme music in the Toki core, while other audio tracks appear unaffected. A similar crackle is also present when flying enemies are destroyed, which is not present on the original hardware. The issue is labeled as 'help wanted'.

This issue proposes to expose several key internal metrics from the GPL (Global Placement) tool to a metrics dashboard. Currently, these metrics are only available in log files. The implementation involves adding calls to `logger_->metric()` for each relevant metric, which is described as straightforward.

This issue aims to improve the isolation of tests within the CTS (Common Test Suite) by removing dependencies on external Detailed Placement (DPL) and Global Placement (GPL) commands. The goal is to ensure that CTS tests can run independently without relying on the output of these other tools, by generating necessary DEF files internally.

This issue proposes to improve the isolation of regression tests by preventing them from unnecessarily invoking upstream tools. The suggested solution is to generate intermediate ODB or DEF files that can be directly used as input for target tool regression tests, thereby reducing maintenance overhead and test fragility.

The current RAM tests generate overly detailed LEF files with specific obstructions, which is inefficient. The issue proposes using a flag (`-bloat_occupied_layers`) to create simpler LEF files with whole-layer obstructions, reducing complexity and improving test efficiency.