The-OpenROAD-Project/OpenROAD

enhancement help wanted In Progress ram

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

ram: bloat occupied layers in test lefs 4 days ago

AI Summary: The current RAM tests generate overly detailed LEF files with specific obstructions, which is inefficient. The issue proposes using a flag (`-bloat_occupied_layers`) to create simpler LEF files with whole-layer obstructions, reducing complexity and improving test efficiency.

Complexity: 2/5

good first issue ram

The-OpenROAD-Project/OpenROAD

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

Create an IP Checker Utility 7 days ago

enhancement good first issue

The-OpenROAD-Project/OpenROAD

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

Multi-cut vias are not yet supported in the detail router 25 days ago

enhancement help wanted drt

The-OpenROAD-Project/OpenROAD

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

Add some good examples from antonblanchard/vlsiffra as a regression test / benchmark about 1 month ago

good first issue

The-OpenROAD-Project/OpenROAD

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

Grammar railroad diagram about 1 month ago

documentation good first issue

The-OpenROAD-Project/OpenROAD

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

Add library of useful functions for doing manual placement of cells about 1 month ago

good first issue

The-OpenROAD-Project/OpenROAD

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

Add support for limiting heatmaps to selection about 1 month ago

good first issue gui

The-OpenROAD-Project/OpenROAD

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

openroad should write it's commands into the log about 1 month ago

good first issue

The-OpenROAD-Project/OpenROAD

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

Use standard naming for variables (ie snake case) in LEF58 parsers about 1 month ago

good first issue

The-OpenROAD-Project/OpenROAD

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

ODB swig python API getPoint about 1 month ago

good first issue

The-OpenROAD-Project/OpenROAD

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

Long running OR commands should report their runtime about 1 month ago

good first issue

The-OpenROAD-Project/OpenROAD

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

ORD Terminal: Pressing TAB to list files & dirs outputs an error 4 months ago

good first issue

The-OpenROAD-Project/OpenROAD

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

feature request: open odb file from the command line 7 months ago

good first issue

The-OpenROAD-Project/OpenROAD

2.5K

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog

#cpp#def#eda#gdsii#lef#opendb-database#openroad#rtl#tcl#timing-analysis#verilog

Open Issues Need Help