chili-chips-ba

chili-chips-ba/openCologne

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com

1 good first / help-wanted issue · Verilog · last activity Oct 22, 2026

107 stars 9 forks 107 watchers Verilog BSD 3-Clause "New" or "Revised" License
colognechip edubos5 fpga gatemate pcb risc-v rtl serdes soc systemverilog
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1 Open Issue Need Help Last updated: Oct 22, 2026

Open Issues Need Help

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Yosys LUT primitives translation into CC primitives -- potentially underperforming? 13 days ago
good first issue benchmarking PrjPeppercorn
chili-chips-ba/openCologne
107

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com

Verilog
#colognechip#edubos5#fpga#gatemate#pcb#risc-v#rtl#serdes#soc#systemverilog